CY7C1386CV25

The CY7C1386CV25/CY7C1387CV25 SRAM integrates 524,288 x 36 and 1048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3 [2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip of CY7C1386CV25/CY7C1387CV25 are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

Address, data inputs, and write controls of  CY7C1386CV25/CY7C1387CV25 are registered on-chip to initiate a self-timed Write cycle.CY7C1383C supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. CY7C1383C incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance.

The CY7C1386CV25/CY7C1387CV25 operates from a +2.5V power supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.