CY7C1386B

Features:

• Fast clock speed: 200, 167, 150, 133 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns
• Optimal for depth expansion
• 3.3V (5% / +10%) power supply
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Double-cycle deselect
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write cycle
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down available using ZZ mode or CE deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
• Automatic power down available using ZZ mode or CE deselect


Pinout




Specifications

Storage Temperature ....................................................................  55°C to +150°C
Ambient Temperature with Power Applied.....................................  55°C to +125°C
Supply Voltage on V_DD Relative to GND ........................................  0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State^[13] .......................................................................  0.5V to V_DDQ + 0.5V
DC Input Voltage^[13] ...................................................................  0.5V to V_DDQ + 0.5V
Current into Outputs (LOW) ........................................................  20 mA
Static Discharge Voltage ..............................................................  >1500V (per MIL-STD-883, Method 3015)
Latch-Up Current .........................................................................  >200 m A


Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.

The CY7C1386B and CY7C1387B SRAMs integrate 524,288 * 36 and 1,048,576 * 18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, data inputs, address-pipelining Chip Enables (CEs), burst control inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). DQ_a,b,c,d and DP_a,b,c,d apply to CY7C1386B and DQ_a,b and DP_a,b apply to CY7C1387B. a, b, c, and d each are 8 bits wide in the case of DQ and 1 bit wide in the case of DP.

Addresses and chip-enables of  CY7C1386B and CY7C1387B  are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV).

Address, data inputs, and write controls of  CY7C1386B and CY7C1387B are registered on-chip to initiate self-timed Write cycles. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DQPa. BWb controls DQ_b and DQP_b. BWc controls DQc and DQPd. BWd controls DQdDQd and DQPd. BWa, BWb, BWc, and BWd can be active only with BWE LOW. GW LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the immediately next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance.

The CY7C1386B and CY7C1387B are both double-cycle deselect parts. All inputs and outputs of the CY7C1386B and the CY7C1387B are JEDEC-standard JESD8-5-compatible.