CY7C1382F

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include
all addresses, all data inputs, address-pipelining chip enable (CE₁), depth-expansion chip enables (CE₂ and CE₃^[2]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX,and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

Addresses and chip-enables of CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F are registered at rising edge of clock when address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as they are controlled by the advance pin (ADV).

Address, data inputs, and write controls of CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F  are registered on-chip to initiate a self-timed write cycle.CY7C1382F supports byte write operations (see Pin Definitions on page 6 and Truth Table [4,5, 6, 7, 8] on page 9 for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F operates from a +3.3V core power supply while all outputs operate with a +2.5 or +3.3V power supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.