Features: • Fast clock speed: 200, 167, 150, 133 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns
• Optimal for depth expansion
• 3.3V (5% / +10%) power supply
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down available using ZZ mode or CE deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging versionPinout
Specifications(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied............................................. 55°C to +125°C
Supply Voltage on VDD Relative to GND ....... 0.3V to +4.6V
DC Voltage Applied to Outputs
in High Z State[9] ................................. 0.5V to VDDQ + 0.5V
DC Input Voltage[9] ............................. 0.5V to VDDQ + 0.5V
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage .......................................... >1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mADescriptionThe Cypress Synchronous Burst SRAM CY7C1380B and CY7C1382B family employs high-speed, low-power CMOS designs using advanced single- layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.
The CY7C1380B and CY7C1382B SRAMs integrate 524,288x36 and 1,048,576x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). DQa,b,c,d and DPa,b,c,d apply to CY7C1380B and DQa,b and DPa,b apply to CY7C1382B. a, b, c, d each are 8 bits wide in the case of DQ and 1 bit wide in the case of DP.
Addresses and chip CY7C1380B and CY7C1382B enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls of CY7C1380B and CY7C1382B are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPc. BWd controls DQd and DPd. BWa, BWb, BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. WRITE pass-through capability CY7C1380B and CY7C1382B allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance.
All inputs and outputs of the CY7C1380B and the CY7C1382B are JEDEC standard JESD8-5 compatible.
CY7C1382B Data Sheet
