CY7C1381F

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs of CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining chip enable (CE₁), depth-expansion chip enables (CE₂ and CE₃ ^[2]), burst control inputs (ADSC, ADSP, and ADV), write enables (BW_x, and BWE), and global write (GW). Asynchronous inputs of CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F include the output enable (OE) and the ZZ pin.

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F allows interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses of CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs.

Address advancement of CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is controlled by the address advancement (ADV) input.

Addresses and chip of CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses of CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F can be internally generated as controlled by the advance pin (ADV).

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F operates from a +3.3V core power supply while all outputs operate with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.