CY7C1381D

The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1M x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs of CY7C1381D/CY7C1383D are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE₁), depth-expansion Chip Enables (CE₂ and CE₃ ^[2]), Burst Control inputs (ADSC,ADSP, and ADV), Write Enables (BW_x, and BWE), and Global Write (GW). Asynchronous inputs of CY7C1381D/CY7C1383D include the Output Enable (OE) and the ZZ pin.

The CY7C1381D/CY7C1383D allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement CY7C1381D/CY7C1383D is controlled by the Address Advancement (ADV) input.

Addresses and chip of CY7C1381D/CY7C1383D enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

The CY7C1381D/CY7C1383D operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.