Features: • Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 2.5V core power supply
• Fast clock-to-output times, 2.6 ns (for 250-MHz device)
• Provides high-performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• CY7C1380DV25/CY7C1382DV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package.
CY7C1380FV25/CY7C1382FV25 available in Pb-free and non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode optionSpecificationsExceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested.
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied.............................................55°C to +125°C
Supply Voltage on VDD Relative to GND ........... 0.3V to +3.6V
Supply Voltage on VDDQ Relative to GND.......... 0.3V to +VDD
DC Voltage Applied to Outputs
in Tri-State............................................. 0.5V to VDDQ + 0.5V
DC Input Voltage .................................... 0.5V to VDD + 0.5V
Current into Outputs (LOW) .......................................... 20 mA
Static Discharge Voltage.............................................. >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... >200 mADescriptionThe CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs of CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 include all addresses, all data inputs, address-pipelining chip enable (CE1), depth expansion chip enables (CE2 and CE3 [2]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs of CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 include the output enable (OE) and the ZZ pin.
Addresses and chip of CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses of CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 can be internally generated as controlled by the advance pin (ADV).
Address, data inputs, and write controls CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 are registered on-chip to initiate a self timed write cycle.This part supports byte write operations (see Pin Definitions on page 6 and Truth Table [4,5, 6, 7, 8] on page 9 for further details). Write cycles of CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written.
The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 operates from a +2.5V core power supply while all outputs may operate with a +2.5 supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.
CY7C1380FV25 Data Sheet
