Features: • Fast clock speed: 200,166, 150, 133 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns
• Optimal for depth expansion
• 2.5V (±5%) Operation
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed WRITE CYCLE
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down for portable applications
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging versionPinout
SpecificationsStorage Temperature .................................55°C to +150°C
Ambient Temperature with
Power Applied .............................................55°C to +125°C
Supply Voltage on VDD Relative to GND.......... 0.3V to +4.6V
DC Voltage Applied to Outputs
n High Z State....................................... 0.5V to VDDQ + 0.5V
DC Input Voltage.................................. 0.5V to VDDQ + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mADescriptionThe Cypress Synchronous Burst SRAM CY7C1382BV25 and CY7C1380BV25 family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.
The CY7C1382BV25 and CY7C1380BV25 SRAMs integrate 1,048,576x18 and 524,288x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs of CY7C1382BV25 and CY7C1380BV25 include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP , and ADV), Write Enables (BWa, BWb, BWc, BWd and BWE), and global write (GW).
Asynchronous inputs of CY7C1382BV25 and CY7C1380BV25 include the output enable (OE) and Burst Mode Control (MODE). The data (DQa,b,c,d) and the data parity (DQPa,b,c,d) outputs, enabled by OE, are also asynchronous.
DQa,b,c,d and DQPa,b,c,d apply to CY7C1380BV25 and DQa,b and DQPa,b apply to CY7C1382BV25. a, b, c, d each are of 8 bits wide in the case of DQ and 1 bit wide in the case of DP.
Addresses and chip CY7C1382BV25 and CY7C1380BV25 enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls of CY7C1382BV25 and CY7C1380BV25 are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DQPa. BWb controls DQb and DQPb. BWc controls DQc and DQPd. BWd controls DQd-DQd and DQPd. BWa, BWb BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. CY7C1382BV25 and CY7C1380BV25 also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance.
All inputs and outputs of the CY7C1380BV25 and the CY7C1382BV25 are JEDEC standard JESD8-5 compatible.
CY7C1380BV25 Data Sheet
