Features: •Pin-compatible and functionally equivalent to ZBT™
•Supports 250-MHz bus operations with zero wait states
-Available speed grades are 250, 225, 200, and 167MHz
•Internally self-timed output buffer control to eliminate the need to use asynchronous OE
•Fully registered (inputs and outputs) for pipelined operation
•Byte Write capability
•Single 3.3V power supply
•3.3V/2.5V I/O power supply
•Fast clock-to-output times
-2.6 ns (for 250-MHz device)
-2.8 ns (for 225-MHz device)
-3.0 ns (for 200-MHz device)
-3.4 ns (for 167-MHz device)
•Clock Enable (CEN) pin to suspend operation
•Synchronous self-timed writes
•Available in lead-Free 100 TQFP, 119 BGA, and 165 fBGA packages
•IEEE 1149.1 JTAG Boundary Scan
•Burst capability-linear or interleaved burst order
•"ZZ" Sleep Mode option and Stop Clock optionPinout
Specifications(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied...........................................55°C to +125°C
Supply Voltage on VDD Relative to GND........0.5V to +4.6V
DC to Outputs in Tri-State...................0.5V to VDDQ + 0.5V
DC Input Voltage....................................0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Description The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and1Mbit x 18 Synchronous pipelined burst SRAMs with No BusLatency™ (NoBL™) logic, respectively. They are designed tosupport unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370D and CY7C1372D are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being trans-ferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370D and CY7C1372D are pin compatible and functionally equivalent to ZBT devices.All synchronous inputs pass through input registers controlled by the rising edge of the clock.
All data outputs of CY7C1370D and CY7C1372D pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal,which when deasserted suspends operation and extends the previous clock cycle.
Write operations of CY7C1370D and CY7C1372D are controlled by the Byte Write Selects(BWaBWd for CY7C1370D andBWaBWb for CY7C1372D) and a Write Enable (WE) input. All writes are conducted withon-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables CY7C1370D and CY7C1372D(CE1,CE2 ,CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid buscontention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
CY7C1372D-225AXI Data Sheet
