CY7C1371DV25

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero wait states
   - Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 2.5V core power supply
• 2.5V I/O power supply
• Fast clock-to-output times
   - 6.5 ns (for 133-MHz device)
   - 8.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-pin TQFP,lead-free and non-lead-free 119-ball BGA and 165- ball FBGA package.
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ mode or CE deselect
• JTAG boundary scan for BGA and FBGA packages
• Burst Capability-linear or interleaved burst order
• Low standby power

The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x 36/1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371DV25/CY7C1373DV25 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs of CY7C1371DV25/CY7C1373DV25 pass through input registers controlled by the rising edge of the clock. The clock input of CY7C1371DV25/CY7C1373DV25 is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.Maximum access delay from the clock rise is 6.5 ns (133-MHz device).

Write operations of CY7C1371DV25/CY7C1373DV25 are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE2, CE₃) and an asynchronous Output Enable CY7C1371DV25/CY7C1373DV25(OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers CY7C1371DV25/CY7C1373DV25 are synchronously tri-stated during the data portion of a write sequence.