CY7C1371B

The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18 synchronous flow-thru burst SRAMs, respectively designed to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The CY7C1371B/ CY7C1373B is equipped with the advanced No Bus Latency™ (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. CY7C1371B/CY7C1373B feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions.|

The CY7C1371B/CY7C1373B is pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock.The clock input of CY7C1371B/CY7C1373B is qualified by the Clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 7.5 ns (117-MHz device). Write operations are controlled by the byte Write Selects (BWSa,b,c,d for CY7C1371B and BWSa,b for CY7C1373B) and a Write enable (WE) input.

All writes of CY7C1371B/CY7C1373B are conducted with on-chip synchronous self-timed Write circuitry. ZZ may be tied to LOW if it is not used. Synchronous Chip enables (CE₁, CE₂, CE₃ on the TQFP, CE₁ on the BGA) and an asynchronous Output enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously CY7C1371B/CY7C1373B three-stated during the data portion of a Write sequence.