CY7C1370CV25-167AC

The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370CV25 and CY7C1372CV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. CY7C1370CV25 and CY7C1372CV25 feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370CV25 and CY7C1372CV25 are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs of CY7C1370CV25 and CY7C1372CV25 pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by t he rising edge of the clock. The clock input of CY7C1370CV25 and CY7C1372CV25 is qualified by the Clock Enable (CEN ) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects(BW _aBW _d for CY7C1370CV25 and BWaBWb forCY7C1372CV25) and a Write Enable (WE ) input. All writes are conducted with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE ₁, CE ₂, CE ₃) and an asynchronous Output Enable (OE ) provide for easy bank selection and output three-state co ntrol. In order to avoid bus contention, the output drivers CY7C1370CV25 and CY7C1372CV25  are synchronously three-stated during the data portion of a write sequence.