CY7C1366C

The CY7C1366C/CY7C1367C SRAM integrates 512K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs of CY7C1366C/CY7C1367C include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE₂ and CE₃ ^[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWA,BWB, BWC, BWD, and BWE), and Global Write (GW).Asynchronous inputs of CY7C1366C/CY7C1367C include the Output Enable (OE) and the ZZ pin.

Addresses and chip CY7C1366C/CY7C1367C enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

Address, data inputs, and write controls of CY7C1366C/CY7C1367C are registered on-chip to initiate a self-timed Write cycle. This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.CY7C1366C/CY7C1367C feature allows depth expansion without penal izing system performance.

The CY7C1368C operates from a +3.3V core power supply and a +3.3V supply for the I/Os. All inputs and outputs are
JEDEC-standard JESD8-5-compatible.