CY7C1365V25

The CY7C1361V25, CY7C1365V25 and CY7C1363V25 are 2.5v, 256K x 36, 256K x 32 and 512K x 18 synchronousflowthrough SRAM designed to interface with high-speed microprocessors with minimal glue logic. Maximum access delay from the clock rise is 7.5 ns (117-MHz device). A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

The CY7C1361V25/CY7C1365V25/CY7C1363V25 supports either the interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses of CY7C1361V25, CY7C1365V25 and CY7C1363V25 can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. Byte write operations are qualified with the Byte Write Select (BW_a,b,c,d for CY7C1361V25/CY7C1365V25 and BW_a,b for CY7C1363V25) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data of CY7C1361V25, CY7C1365V25 and CY7C1363V25 to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) of CY7C1361V25, CY7C1365V25 and CY7C1363V25 and an asynchronous output enable (OE) provide for easy bank selection and output three-state control.