Features: • Supports bus operation up to 225 MHz
• Available speed grades are 225, 200 and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
- 2.8 ns (for 225-MHz device)
- 3.0 ns (for 200-MHz device)
- 3.5 ns (for 166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting IntelPentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary ScanSpecifications(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .......................................................................65°C to +150°C
Ambient Temperature with
Power Applied...................................................................................55°C to +125°C
Supply Voltage on VDD Relative to GND................................................. 0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ............................................................................ ..0.5V to VDDQ + 0.5V
DC Input Voltage..............................................................................0.5V to VDD + 0.5V
Current into Outputs (LOW)................................................................................... 20 mA
Static Discharge Voltage...................................................................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current................................................................................................ >200 mADescription
The CY7C1360B/CY7C1362B SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs of CY7C1360B/CY7C1362B include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs of CY7C1360B/CY7C1362B include the Output Enable (OE) and the ZZ pin.
Addresses and chip CY7C1360B/CY7C1362B enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).
Address, data inputs, and write controls of CY7C1360B/CY7C1362B are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written.
The CY7C1360B/CY7C1362B operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
CY7C1362B Data Sheet
