CY7C136

Features:

* True Dual-Ported memory cells which allow simulta- neous reads of the same memory location
* 2K x 8 organization
* 0.65-micron CMOS for optimum speed/power
* High-speed access: 15 ns
* Low operating power: I_CC   = 90 mA (max.)
* Fully asynchronous operation
* Automatic power-down
* Master CY7C132/CY7C136 easily expands data bus  width to 16 or more bits using slave CY7C142/CY7C146
* BUSY output flag on CY7C132/CY7C136; BUSY input  on CY7C142/CY7C146
* INT flag for port-to-port communication (52-pin  PLCC/PQFP versions)
* Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and  52-pin TQFP (CY7C136/146)
* Pin-compatible and functionally equivalent to  IDT7132/IDT7142


Pinout




Specifications

(Above which the useful life may be impaired. For user guide- lines, not tested.)
Storage Temperature ........................................-65°C to +150°C
Ambient Temperature with
Power Applied....................................................-55°C to +125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24)......................................................-0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State..........................................................-0.5V to +7.0V
DC Input Voltage......................................................-3.5V to +7.0V
Output Current into Outputs (LOW)......................................20 mA
Static Discharge Voltage.................................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.............................................................. >200 mA


Description

The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132/ CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER du- al-port RAM in  conjunction with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port of CY7C132/CY7C136/CY7C142 and CY7C146 has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY sig- nals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data of CY7C132/CY7C136/CY7C142 and CY7C146 has been placed in a unique location (7FF for the left port and 7FE for the right port).

An automatic power-down CY7C132/CY7C136/CY7C142 and CY7C146 feature is controlled independently on each port by the chip enable (CE) pins.

The CY7C132/CY7C142 are available in 48-pin DIP. The CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.