CY7C1356B

• Pin-compatible and functionally equivalent to ZBT
• Supports 225-MHz bus operations with zero wait states
   - Available speed grades are 225, 200, and 166 MHz
• Internally self-timed output buffer control to eliminatethe need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• Separate VDDQ for 3.3V or 2.5V I/O
• Single 3.3V power supply
• Fast clock-to-output times
   - 2.8 ns (for 225-MHz device)
   - 3.2ns (for 200-MHz device)
   - 3.5 ns (for 166-MHz device)
• Clock Enable ( CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capabilitylinear or interleaved burst order
• "ZZ" Sleep Mode option and Stop Clock option

The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and512K x 18 Synchronous pipelined burst SRAMs with No BusLatency™ (NoBL^TM) logic, respectively. They are designed tosupport unlimited true back-to-back Read/Write operationswith no wait states. The CY7C1354B and CY7C1356B areequipped with the advanced (NoBL) logic required to enableconsecutive Read/Write operations with data being transferredon every clock cycle. This feature dramatically improvesthe throughput of data in systems that require frequentWrite/Read transitions. The CY7C1354B and CY7C1356B arepin compatible and functionally equivalent to ZBT devices.

All synchronous inputs of CY7C1354B and CY7C1356B pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock. Theclock input of CY7C1354B and CY7C1356B is qualified by the Clock Enable ( CEN) signal,which when deasserted suspends operation and extends theprevious clock cycle.

Write operations of CY7C1354B and CY7C1356B are controlled by the Byte Write Selects(BW_aBW_d for CY7C1354B and BW_aBW_b for CY7C1356B)
and a Write Enable (WE) input. All writes are conducted withon-chip synchronous self-timed write circuitry.

Three synchronous CY7C1354B and CY7C1356B Chip Enables (CE ₁, CE₂, CE ₃) and anasynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid buscontention, the output drivers CY7C1354B and CY7C1356B are synchronously three-statedduring the data portion of a write sequence.