CY7C1354CV25

• Pin-compatible with and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
• Available speed grades are 250, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• Single 2.5V power supply
• Fast clock-to-output times
   - 2.8 ns (for 250-MHz device)
   - 3.2 ns (for 200-MHz device)
   - 3.5 ns (for 166-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in lead-free 100-pin TQFP package, lead-free and non lead-free 119-ball BGA package and 165-ball FBGA package
• IEEE 1149.1 JTAG Boundary Scan
• Burst capabilitylinear or interleaved burst order
• "ZZ" Sleep Mode option and Stop Clock option

The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354CV25 and CY7C1356CV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1354CV25 and CY7C1356CV25 are pin-compatible with and functionally equivalent to ZBT devices.

All synchronous inputs of CY7C1354CV25 and CY7C1356CV25 pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input of CY7C1354CV25 and CY7C1356CV25 is qualified by the Clock Enable (CEN) signal,which when deasserted suspends operation and extends the previous clock cycle.

Write operations of CY7C1354CV25 and CY7C1356CV25 are controlled by the Byte Write Selects (BW_aBW_d for CY7C1354CV25 and BW_aBW_b for CY7C1356CV25) and a Write Enable (WE) input. All writes of CY7C1354CV25 and CY7C1356CV25 are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CY7C1354CV25 and CY7C1356CV25(CE₁, CE2, CE₃) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers CY7C1354CV25 and CY7C1356CV25 are synchronously tri-stated during the data portion of a write sequence.