CY7C1352F

• Pin compatible and functionally equivalent to ZBT™devices
• Internally self-timed output buffer control to eliminatethe need to use OE
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• 2.5V / 3.3V I/O Operation
• Fast clock-to-output times
   - 2.6 ns (for 250-MHz device)
   - 2.6 ns (for 225-MHz device)
   - 2.8 ns (for 200-MHz device)
   - 3.5 ns (for 166-MHz device)
   - 4.0 ns (for 133-MHz device)
   - 4.5 ns (for 100-MHz device)
• Clock Enable (CEN ) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE )
• JEDEC-standard 100 TQFP package
• Burst Capability-linear or interleaved burst order
• "ZZ" Sleep Mode Option and Stop Clock option

(Above which the useful life may be impaired. For user guidelines,not tested.)
Storage Temperature ..................................... −65 to +150
Ambient Temperature with
Power Applied..................................................−55 to +125
Supply Voltage on V_DD Relative to GND.............−0.5V to +4.6V
DC Voltage Applied to Outputs
in three-state ........................................ −0.5V to V_DDQ + 0.5V
DC Input Voltage ......................................−0.5V to V_DD + 0.5V
Current into Outputs (LOW)............................................ 20 mA
Static Discharge Voltage.............................................. > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................... > 200 mA

The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelinedBurst SRAM designed specifically to support unlimited trueback-to-back Read/Write operations without the insertion ofwait states. The CY7C1352F is equipped with the advancedNo Bus Latency™ (NoBL™) logic required to enable consecutiveRead/Write operations with data being transferred onevery clock cycle. This feature dramatically improves thethroughput of the SRAM, especially in systems that requirefrequent Write/Read transitions.

All synchronous inputs of CY7C1352F pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock. Theclock input is qualified by the Clock Enable (CEN) signal,which, when deasserted, suspends operation and extends theprevious clock cycle. Maximum access delay from the clockrise is 2.8 ns (200-MHz device)

Write operations of CY7C1352F are controlled by the two Byte Write Select(BW_[A:B]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an
asynchronous Output Enable (OE)of CY7C1352F provide for easy bankselection and output three-state control. In order to avoid buscontention, the output drivers are synchronously three-statedduring the data portion of a write sequence.