CY7C1352B

Features:

• Pin compatible and functionally equivalent to ZBT™ 
   devices MCM63Z818 and MT55L256L18P
• Supports 166-MHz bus operations with zero wait states
    -Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
   the need to use OE
• Fully registered (inputs and outputs) for pipelined
   operation
• Byte Write Capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times 
   -3.5 ns (for 166-MHz device)
   -3.8 ns (for 150-MHz device)
   -4.0 ns (for 143-MHz device)
   -4.2 ns (for 133-MHz device)
   -5.0 ns (for 100-MHz device)
   -7.0 ns (for 80-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP package
• Burst Capability-linear or interleaved burst order


Pinout




Description

The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Read/Write transitions. The CY7C1352B is pin/functionally compatible to ZBT SRAMs MCM63Z819 and MT55L256L18P.

All synchronous inputs of CY7C1352B pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input of CY7C1352B is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 3.5 ns (166-MHz device).