CY7C1346

The CY7C1346 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when V_DDQ=2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs of CY7C1346 pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.5 ns (166-MHz device).

The CY7C1346 supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence CY7C1346 is controlled by the ADV input. A 2-bit on-chip wraparound burstm counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte write operations of CY7C1346 are qualified with the four Byte Write Select (BW_[3:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) CY7C1346 and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state.