Features: • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32P• Supports 133-MHz bus operations with zero wait states -Data is transferred on every clock• Internally self-timed output buffer control to eliminate the need to use OE• Fully registered ...
CY7C1334: Features: • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32P• Supports 133-MHz bus operations with zero wait states -Data is transferred on every clock• ...
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The CY7C1334 is a 3.3V, 64K by 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write-Read transitions.The CY7C1334 is pin/functionally compatible to ZBT SRAM MT55L64L32P
All synchronous inputs of CY7C1334 pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input of CY7C1334 is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 4.2 ns (133-MHz device).
Write operations of CY7C1334 are controlled by the four Byte Write Selects (BWS[0-3]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE)of CY7C1334 provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers CY7C1334 are synchronously three-stated during the data portion of a write sequence.