CY7C1330

The CY7C1330 is 3.3V 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

All synchronous inputs of CY7C1330 pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 5 ns (117-MHz version). A 2-bit on-chip wraparound burst counter CY7C1330 captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

The CY7C1330 supports either the interleaved burst sequence or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the processor address strobe (ADSP) or the controller address strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. Byte write operations of CY7C1330 are qualified with the four Byte Write Select (BW_[0-3]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous chip of CY7C1330 selects (CE₁, CE₂, CE₃) and an asynchronous output enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data
during depth expansion, OE is masked during the first clock of a read cycle when going from a deselected to a selected state.