CY7C1319BV18

Features: • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)• 300-MHz clock for high bandwidth• 4-Word burst for reducing address bus frequency• Double Data Rate (DDR) interfaces (data transferred at 600MHz) @ 300 MHz• Two input clocks (K and K) for precise DDR ti...

product image

CY7C1319BV18 Picture
SeekIC No. : 004319919 Detail

CY7C1319BV18: Features: • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)• 300-MHz clock for high bandwidth• 4-Word burst for reducing address bus frequency• Double Data Rate (DDR) in...

floor Price/Ceiling Price

Part Number:
CY7C1319BV18
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/12/21

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
• 300-MHz clock for high bandwidth
• 4-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 600MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4VVDD)
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both lead-free and non-lead free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement



Specifications

(Above which the useful life may be impaired.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with Power Applied ....10°C to +85°C
Supply Voltage on VDD Relative to GND............ 0.5V to +2.9V
DC Applied to Outputs in High-Z.............. 0.5V to VDDQ + 0.3V
DC Input Voltage[13] .............................. 0.5V to VDDQ + 0.3V
Current into Outputs (LOW)............................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015)............ > 2001V
Latch-up Current.......................................................... > 200 mA



Description

The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II (Double Data Rate) architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with four 8-bit words in the case of CY7C1317BV18 and four 9-bit words in the case of CY7C1917BV18 that burst sequentially into or out of the device. The burst counter always starts with "00" internally in the case of CY7C1317BV18 and CY7C1917BV18. On CY7C1319BV18 and CY7C1321BV18, the burst counter takes in the last two significant bits of the external address and bursts four 18-bit words in the case of CY7C1319BV18, and four 36-bit words in the case of CY7C1321BV18, sequentially into or out of the device.

Asynchronous inputs of CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 include output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR-II SRAM CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.

All synchronous inputs of CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
Semiconductor Modules
Test Equipment
Industrial Controls, Meters
Transformers
Memory Cards, Modules
View more