CY7C1306BV18

• Separate independent Read and Write data ports
- Supports concurrent transactions
• 167-MHz Clock for high bandwidth
   - 2.5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
   - SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew and flight time mismatching
• Single multiplexed address input bus latches address inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V1.9V)
• JTAG Interface
• Variable Impedance HSTL

The CY7C1303BV18 and CY7C1306BV18 are 1.8V Synchronous Pipelined SRAMs equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR architecture has separate data inputs and data outputs of CY7C1303BV18 and CY7C1306BV18 to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the device's Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports of CY7C1303BV18 and CY7C1306BV18 are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 18-bit words (CY7C1303BV18) and four 36-bit words (CY7C1306BV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the CY7C1303BV18 and CY7C1306BV18 on every rising edge of both input clocks (K/K and C/C) memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds."

Depth expansion of CY7C1303BV18 and CY7C1306BV18 is accomplished with Port Selects for each port. Port selects allow each port to operate  ndependently.

All synchronous inputs of CY7C1303BV18 and CY7C1306BV18 pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers CY7C1303BV18 and CY7C1306BV18 controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.