CY7C1304V25

The CY7C1304V25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations.

QDR architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the CY7C1304V25 Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location of CY7C1304V25 is associated with 4 18-bit words that burst sequentially into or out of CY7C1304V25. Since data can be transferred into and out of the device on every rising edge of both input clocks (K/K and C/C) memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds".

Depth expansion of CY7C1304V25 is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by theK orK input clocks. All data outputs pass through output registers CY7C1304V25 controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.