CY7C1302V25

The CY7C1302V25 is a 2.5V Synchronous-Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Accesses to the CY7C1302V25 Read and Write ports are completely independent of one another. All accesses of CY7C1302V25 are initiated synchronously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Therefore, data of CY7C1302V25 can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C) thereby maximizing performance while simplifying system design.

Depth expansion of CY7C1302V25 is accomplished with a Port Select input for each port. Each Port Selects allow each port to operate independently.

All synchronous inputs of CY7C1302V25 pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.