CY7C1302CV25

The CY7C1302CV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR CY7C1302CV25 has separate data inputs and data outputs to completely eliminate the need to "turn-around"the data bus required with common I/O devices. Accesses to the CY7C1302CV25 Read and Write ports are completely independent of one another. All accesses of CY7C1302CV25 are initiated synchronously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and
Write ports are equipped with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C, or K and K in a single clock domain) thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words that burst sequentially into or out of CY7C1302CV25.

Depth expansion of CY7C1302CV25 is accomplished with a Port Select input for each port. Each Port Select allows each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs of CY7C1302CV25 pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes of CY7C1302CV25 are conducted with on-chip synchronous self-timed write circuitry.