CY7C130-35PC

Features: • True Dual-Ported memory cells which allow simultaneous reads of the same memory location• 1K x 8 organization• 0.65-micron CMOS for optimum speed/power• High-speed access: 15 ns• Low operating power: ICC = 90 mA (max.)• Fully asynchronous operation&#...

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SeekIC No. : 004319869 Detail

CY7C130-35PC: Features: • True Dual-Ported memory cells which allow simultaneous reads of the same memory location• 1K x 8 organization• 0.65-micron CMOS for optimum speed/power• High-spee...

floor Price/Ceiling Price

Part Number:
CY7C130-35PC
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

• True Dual-Ported memory cells which allow simultaneous
  reads of the same memory location
• 1K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 90 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C130/CY7C131 easily expands data bus
  width to 16 or more bits using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/CY7C131; BUSY input
  on CY7C140/CY7C141
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and
  52-pin TQFP
• Pin-compatible and functionally equivalent to
  IDT7130/IDT7140



Pinout

  Connection Diagram


Specifications

(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................................. 65°C to +150°C
Ambient Temperature with
Power Applied............................................. 55°C to +125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V
DC Input Voltage............................................ 3.5V to +7.0V
Output Current into Outputs (LOW) .............................20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Notes:
3. 15 and 25-ns version available only in PLCC/PQFP packages.
4. Shaded area contains preliminary information.
5. TA is the "instant on" case temperature



Description

The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port of CY7C130-35PC is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power-down feature of CY7C130-35PC is controlled independently on each port by the chip enable (CE) pins.

The CY7C130 and CY7C140 are available in 48-pin DIP. The CY7C131 and CY7C141 are available in 52-pin PLCC and PQFP.




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