CY7C1298H

The CY7C1298H SRAM integrates 64K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs of CY7C1298H are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip Enables (CE and CE ), Burst 1 2 3 , ADSP, and ADV), Write Enables Control inputs (ADSC (BW , and BWE), and Global Write (GW). Asynchronous [A:B] inputs include the Output Enable (OE ) and the ZZ pin.

Addresses and chip of CY7C1298H enables are registered at rising edge of clock when either Address Strobe Processor (ADSP ) or ) are active. Subsequent Address Strobe Controller (ADSC burst addresses can be internally generated as controlled by the Advance pin (ADV ).

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. CY7C1298H incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect of CY7C1298H is executed.This feature allows depth expansion without penal- izing system performance.

The CY7C1298H operates from a +3.3V core power supply while all outputs operate either with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.