CY7C1298A

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced double- layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.

The CY7C1298A/GVT7164C18 SRAM integrates 65536x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive- edge-triggered Clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE₂ and CE₂), burst control inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), and Global Write (). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q)CY7C1298A , enabled by OE, are also asynchronous. Addresses and chip enables of CY7C1298A are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1DQ8 and DQP1. WEH controls DQ9DQ16 and DQP2. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written. CY7C1298A also incorporates Write pass-through capability and pipelined enable circuit for better system performance.

The CY7C1298A/GVT7164C18 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium®, 680x0, and PowerPC™ systems and for systems that are benefited from a wide synchronous data bus.