CY7C1263V18-400BZXC

Organization :
Packaging :
Mounting Style : SMD/SMT
Memory Size : 36 Mbit
Access Time : 0.45 ns
Supply Voltage - Max : 1.9 V
Supply Voltage - Min : 1.7 V
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
Package / Case : FBGA
Maximum Operating Current : 1330 mA


Description

The CY7C1263V18-400BZXC is one member of the CY7C1263V18 series.The CY7C1263V18 is 1.8V Synchronous Pipelined SRAM,equipped with Quad Data Rate-II+ (QDR-II+) architecture.QDR-II+ architecture consists of two separate ports to access the memory array.The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to "turn around" the data bus required with common IO devices.Each port is accessed through a common address bus.Addresses for read and write addresses of CY7C1263V18-400BZXC are latched on alternate rising edges of the input (K) clock.

Features of the CY7C1263V18-400BZXC are:(1)300 MHz to 400 MHz clock for high bandwidth; (2)4-Word Burst for reducing address bus frequency ; (3)double data rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz ; (4)read latency of 2.5 clock cycles ; (5)single multiplexed address input bus latches address inputs for both read and write ports; (6)separate port selects for depth expansion; (7)data valid pin (QVLD) to indicate valid data on the output; (8)synchronous internally self-timed writes; (9)available in x8, x9, x18, and x36 configurations; (10)full data coherency providing most current data.

The absolute maximum ratings of the CY7C1263V18-400BZXC can be summarized as:(1)supply voltage on Vdd relative to GND:-0.5 to 2.9V;(2)storage temperature:-65 to 150;(3)ambient temperature with power applied:-55 to 125;(4)supply voltage on Vddq relative to GND:-0.5 to Vdd V;(5)current into output(low):20mA.Be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, although the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device,but there is no guarantee as to the value that is captured. Repeatable results may not be possible.

Parameters:

Technical/Catalog Information	CY7C1263V18-400BZXC
Vendor	Cypress Semiconductor Corp
Category	Integrated Circuits (ICs)
Memory Type	SRAM - Synchronous
Memory Size	36M (4M x 8)
Speed	400MHz
Interface	Parallel
Package / Case	165-FBGA
Packaging	Tray
Voltage - Supply	1.7 V ~ 1.9 V
Operating Temperature	0°C ~ 70°C
Format - Memory	RAM
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CY7C1263V18 400BZXC CY7C1263V18400BZXC