CY7C1261V18

The CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs, equipped with Quad Data Rate-II+ (QDR-II+) architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to "turn around" the data bus required with common IO devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR-II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1261V18), 9-bit words (CY7C1276V18), 18-bit words (CY7C1263V18), or 36-bit words (CY7C1265V18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds".

Depth expansion is accomplished with Port Selects for each port. Port selects enable each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs of  pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.