CY7C1231F

Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied.............................................55°C to +125°C
Supply Voltage on VDD Relative to GND ...... 0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ..................................... 0.5V to V_DDQ + 0.5V
DC Input Voltage....................................0.5V to V_DD + 0.5V
Current into Outputs (LOW)........................................ 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA

The CY7C1231F is a 3.3V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1231F is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. CY7C1231F feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input ofCY7C1231F is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 7.5 ns (117-MHz device).

Write operations of CY7C1231F are controlled by the two Byte Write Select (BW_[A:B]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus contention, the output drivers CY7C1231F are synchronously three-stated during the data portion of a write sequence.