CY7C123

The CY7C123 is a high-performance CMOS static RAM organized as 256 words by 4 bits. Easy memory expansion is provided by an active LOW chip select one (CS₁) input, an active HIGH chip select two (CS2) input, and three-state outputs.

Writing to CY7C123 is accomplished when the chip select one (CS₁) and write enable (WE) inputs are both LOW and the chip select two input is HIGH. Data on the four data inputs (D0 through D3) is written into the memory location specified on the address pins (A0 through A7). The outputs are preconditioned so that the write data is present at the outputs when the write cycle of CY7C123 is complete. This precondition operation ensures minimum write recovery times by eliminating the "write recovery glitch."

Reading CY7C123 is accomplished by taking the chip select one (CS₁) and output enable (OE) inputs LOW, while the write enable (WE) and chip select two (CS₂) inputs remain HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O0 through O₃).

The output pins of CY7C123 remain in high-impedance state when chip select one (CS₁) or output enable (OE) is HIGH, or write enable (WE) or chip select two (CS₂) is LOW.

A die coat ofCY7C123 is used to insure alpha immunity.