CY7C1223F

The CY7C1223F SRAM integrates 131,072 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs of CY7C1223F, address-pipelining Chip Enable (CE₁), depth-expansion Chip Enables (CE₂ and CE₃), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW_[A:B] and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

Address, data inputs, and write of CY7C1223F  controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. CY7C1223F incorporates an dditional pipelined enable register which delays turning off he output buffers an additional cycle when a deselect is xecuted.This feature allows depth expansion without penalizing ystem erformance.

The CY7C1223F operates from a +3.3V core power supply hile all outputs operate with a +3.3V supply. All inputs and utputs are JEDEC-standard JESD8-5-compatible.