CY7C1218H

The CY7C1218H SRAM integrates 32K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs CY7C1218H (ADSC,ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip of CY7C1218H enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip  to initiate a self-timed Write cycle.This part of CY7C1218H supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1218H operates from a +3.3V core power supply while all outputs may operate either with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.