Features: • High speed -tAA = 15, 20, 25ns• VCC = 3.3V ± 10%• Low active power -432 mW (max.) -288 mW (L version)• Low CMOS standby power -18 mW (max.) -7.2 mW (L version)• 2.0V Data Retention• Automatic power-down when deselected• TTL-compatible inputs an...
CY7C109V33: Features: • High speed -tAA = 15, 20, 25ns• VCC = 3.3V ± 10%• Low active power -432 mW (max.) -288 mW (L version)• Low CMOS standby power -18 mW (max.) -7.2 mW (L version)...
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The CY7C109V33/CY7C1009V33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write Enable (WE) inputs LOW and Chip Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7)of CY7C109V33 is then written into the location specified on the address pins (A0 through A16).
Reading from CY7C109V33 is accomplished by taking Chip Enable one (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when CY7C109V33 is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C109V33 is available in standard 32-pin, 400-mil-wide SOJ package. The CY7C1009V33 is available in a 32-pin, 300-mil-wide SOJ package. The CY7C1009V33 and CY7C109V33 are functionally equivalent in all other respects.