CY7C109D

Features: • Pin- and function-compatible with CY7C109B/CY7C1009B• High speed- tAA = 10 ns• Low active power- ICC = 60 mA @ 10 ns• Low CMOS standby power- ISB2 = 1.2 mA ('L' Version only)• 2.0V Data Retention• Automatic power-down when deselected• TTL-compa...

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CY7C109D Picture
SeekIC No. : 004319827 Detail

CY7C109D: Features: • Pin- and function-compatible with CY7C109B/CY7C1009B• High speed- tAA = 10 ns• Low active power- ICC = 60 mA @ 10 ns• Low CMOS standby power- ISB2 = 1.2 mA ('L' V...

floor Price/Ceiling Price

Part Number:
CY7C109D
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

• Pin- and function-compatible with CY7C109B/CY7C1009B
• High speed
- tAA = 10 ns
• Low active power
- ICC = 60 mA @ 10 ns
• Low CMOS standby power
- ISB2 = 1.2 mA ('L' Version only)
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
• Available in Pb-Free Packages



Pinout

  Connection Diagram


Specifications

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied.............................................55°C to +125°C
Supply Voltage on VCC to Relative GND[2] .... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[2] ....................................0.5V to VCC + 0.5V
DC Input Voltage[2].................................0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA



Description

The CY7C109D/CY7C1009D is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable CY7C109D(WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).

Reading from CY7C109D is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins CY7C109D (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).

The CY7C109D is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009D is available in a 300-mil-wide SOJ Pb-Free package. The CY7C1009D and CY7C109D are functionally equivalent in all other respects.




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