Features: • High speed - tAA = 12 ns• Low active power - 495 mW (max. 12 ns)• Low CMOS standby power - 55 mW (max.) 4 mW• 2.0V Data Retention• Automatic power-down when deselected• TTL-compatible inputs and outputs• Easy memory expansion with CE1, CE2, and...
CY7C109B: Features: • High speed - tAA = 12 ns• Low active power - 495 mW (max. 12 ns)• Low CMOS standby power - 55 mW (max.) 4 mW• 2.0V Data Retention• Automatic power-down when...
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The CY7C109B/CY7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data of CY7C109B on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).
Reading from CY7C109B is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when CY7C109B is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2HIGH, and WE LOW).
The CY7C109B is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package. The CY7C1009B and CY7C109B are functionally equivalent in all other respects.