CY7C109B-12VC

Series: -
Voltage - Supply: 4.5 V ~ 5.5 V
Packaging: Tube
Operating Temperature: 0°C ~ 70°C
Memory Size: 1M (128K x 8)
Format - Memory: RAM
Interface: Parallel
Memory Type: SRAM - Asynchronous
Speed: 12ns
Supplier Device Package: 32-SOJ
Package / Case: 32-BSOJ
Manufacturer: Cypress Semiconductor Corp


Features:

• High speed
-tAA = 12 ns
• Low active power
-495 mW (max. 12 ns)
• Low CMOS standby power
-55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options


Pinout




Specifications

(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied............................................. 55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ...................................0.5V to VCC + 0.5V
DC Input Voltage[1] ...............................0.5V to VCC + 0.5V
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA


Description

The CY7C109B / CY7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to CY7C109B-12VC is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).

Reading from CY7C109B-12VC is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when CY7C109B-12VC is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).

The CY7C109B is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package. The CY7C1009B and CY7C109B are functionally equivalent in all other respects.