Features: • Pin- and function-compatible with CY7C106B/CY7C1006B• High speed- tAA = 10 ns• CMOS for optimum speed/power• Low active power- ICC = 60 mA @ 10 ns• Low CMOS standby power- ISB2 = 3.0 mA• Data Retention at 2.0V• Automatic power-down when deselec...
CY7C106D: Features: • Pin- and function-compatible with CY7C106B/CY7C1006B• High speed- tAA = 10 ns• CMOS for optimum speed/power• Low active power- ICC = 60 mA @ 10 ns• Low CMOS...
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The CY7C106D and CY7C1006D are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected.
Writing to CY7C106D is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17).
Reading from CY7C106D is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when CY7C106D are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW).
The CY7C106D is available in a standard 400-mil-wide Pb-Free SOJ; the CY7C1006D is available in a standard 300-mil-wide Pb-Free SOJ.