CY7C1062AV25

The CY7C1062AV25 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits.

Writing to CY7C1062AV25 is accomplished by enabling the chip (CE₁, CE₂ and CE₃ LOW) and forcing the Write Enable (WE) input LOW. If Byte Enable A (BA) is LOW, then data from I/O pins (I/O₀ through I/O₇), is written into the location specified on the address pins (A₀ through A₁₈). If Byte Enable B (BB) is LOW, then data from I/O pins (I/O₈ through I/O₁₅) CY7C1062AV25 is written into the location specified on the address pins (A₀ through A₁₈). Likewise, BC and BD correspond with the I/O pins I/O₁₆ to I/O₂₃ and I/O₂₄ to I/O₃₁, respectively.

Reading from CY7C1062AV25 is accomplished by enabling the chip (CE₁, CE₂ and CE₃ LOW) while forcing the Output Enable  (OE) LOW and Write Enable (WE) HIGH. If the first Byte Enable (BA) is LOW, then data from the memory location specified by the address pins will appear on I/O₀ to I/O₇. If Byte Enable B (BB) is LOW, then data from memory will appear on I/O₈ to I/O₁₅. Similarly, Bc and BD correspond to the third and  fourth bytes. See the truth table at the back of this data of CY7C1062AV25 sheet for a complete description of read and write modes.

The input/output pins (I/O0 through I/O31) are placed in a high-impedance state when CY7C1062AV25 is deselected (CE₁, CE₂or CE₃ HIGH), the outputs are disabled (OE HIGH), the byte selects are disabled (BA-D HIGH), or during a write operation (CE₁, CE₂ and CE₃ LOW, and WE LOW).

The CY7C1062AV25 is available in a 119-ball pitch ball grid array (PBGA) package.