Features: • High speed -tAA = 12 ns• CMOS for optimum speed/power• Low active power -910 mW• Low standby power -275 mW• 2.0V data retention (optional) -100 mW• Automatic power-down when deselected• TTL-compatible inputs and outputsPinoutSpecifications(Abov...
CY7C106: Features: • High speed -tAA = 12 ns• CMOS for optimum speed/power• Low active power -910 mW• Low standby power -275 mW• 2.0V data retention (optional) -100 mW• Au...
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The CY7C106 and CY7C1006 are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. These devices have an automatic power-down feature of CY7C106 that reduces power consumption by more than 65% when the devices are deselected.
Writing to CY7C106 is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17).
Reading from CY7C106 is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when CY7C106 are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW).
The CY7C106 is available in a standard 400-mil-wide SOJ; the CY7C1006 is available in a standard 300-mil-wide SOJ.