CY7C106

Features: • High speed -tAA = 12 ns• CMOS for optimum speed/power• Low active power -910 mW• Low standby power -275 mW• 2.0V data retention (optional) -100 mW• Automatic power-down when deselected• TTL-compatible inputs and outputsPinoutSpecifications(Abov...

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CY7C106 Picture
SeekIC No. : 004319807 Detail

CY7C106: Features: • High speed -tAA = 12 ns• CMOS for optimum speed/power• Low active power -910 mW• Low standby power -275 mW• 2.0V data retention (optional) -100 mW• Au...

floor Price/Ceiling Price

Part Number:
CY7C106
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/7/15

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Product Details

Description



Features:

• High speed
  -tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
   -910 mW
• Low standby power
   -275 mW
• 2.0V data retention (optional)
   -100 mW
• Automatic power-down when deselected
• TTL-compatible inputs and outputs



Pinout

  Connection Diagram


Specifications

(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .............................. 65°C to +150°C
Ambient Temperature with
Power Applied.......................................... 55°C to +125°C
Supply Voltage on VCC Relative to GND[1] .... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ...................................0.5V to VCC + 0.5V
DC Input Voltage[1]................................0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage ..........................................  >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................  >200 mA



Description

The CY7C106 and CY7C1006 are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. These devices have an automatic power-down feature of CY7C106 that reduces power consumption by more than 65% when the devices are deselected.

Writing to CY7C106 is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17).

Reading from CY7C106 is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins.

The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when CY7C106 are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW).

The CY7C106 is available in a standard 400-mil-wide SOJ; the CY7C1006 is available in a standard 300-mil-wide SOJ.




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