Features: • High speed-tAA = 12 ns• Low active power-1320 mW (max.)• Low CMOS standby power (Commercial L version)-2.75 mW (max.)• 2.0V Data Retention (400 W at 2.0V retention)• Automatic power-down when deselected• TTL-compatible inputs and outputs• Easy ...
CY7C1049B: Features: • High speed-tAA = 12 ns• Low active power-1320 mW (max.)• Low CMOS standby power (Commercial L version)-2.75 mW (max.)• 2.0V Data Retention (400 W at 2.0V retentio...
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The CY7C1049B is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to CY7C1049B is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0through I/O7) is then written into the location specified on the address pins (A0 through A18).
Reading from CY7C1049B is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when CY7C1049B is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW).
The CY7C1049B is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout.