Features: • High speed -tAA = 10 ns• Low active power -1018 mW (max.)• Low CMOS standby power(L version) -2.75 mW (max.)• 2.0V Data Retention (400 µW at 2.0V retention)• Automatic power-down when deselected• TTL-compatible inputs and outputs• Easy me...
CY7C1046: Features: • High speed -tAA = 10 ns• Low active power -1018 mW (max.)• Low CMOS standby power(L version) -2.75 mW (max.)• 2.0V Data Retention (400 µW at 2.0V retention)...
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The CY7C1046 is a high-performance CMOS static RAM organized as 1,048,576 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the fourI/O pins (I/O0 through I/O3) CY7C1046 is then written into the location specified on the address pins (A0 through A19).
Reading from CY7C1046 is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when CY7C1046 is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW).
The CY7C1046 is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolutionary) pinout.