CY7C1020CV26

The CY7C1020CV26 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Writing to CY7C1020CV26 is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O₈), is written into the location specified on the address pins (A₀ through A₁₄). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O₁₆) is written into the location specified on the address pins (A₀ through A₁₄).

Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW CY7C1020CV26 while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O₁ to I/O₈. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O₁₆. See the truth table at the back of this data sheet for a complete description of read and write modes.

The input/output pins (I/O₁ through I/O₁₆) are placed in a high-impedance state when CY7C1020CV26 is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

The CY7C1020CV26 is available in standard 44-pin TSOP Type II.