CY7C09369A

Features:

• True dual-ported memory cells which allow simulta-
   neous access of the same memory location
• Two Flow-Through/Pipelined devices
   -16K x 16/18 organization (CY7C09269A/369A)
• Three Modes
   -Flow-Through
   -Pipelined
   -Burst
• Pipelined output mode on both ports allows fast 100-
   MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5^[1] /7.5/9/12 ns (max.)
• Low operating power
   -Active = 195 mA (typical)
   -Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
   -Shorten cycle times
   -Minimize bus noise
   -Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial temperature range
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to 
   IDT709269


Pinout




Specifications

(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature.................................. 65°C to +150°C
Ambient Temperature with Power Applied..55°C to +125°C
Supply Voltage to Ground Potential................0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State..................................0.5V to +7.0V
DC Input Voltage............................................0.5V to +7.0V
Output Current into Outputs (LOW)..............................20 mA
Static Discharge Voltage.............................................>1100V
Latch-Up Current.......................................................>200 mA


Description

The CY7C09269A and CY7C09369A are high-speed synchronous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports of CY7C09369A  are provided, permitting independent, simultaneous access for reads and writes to any location in memory. ^[4] Registers on control, address, and data lines allow for minimal set- up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid t _CD2  = 6.5 ns ^[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available t_CD1 = 15 ns after the address is clocked into CY7C09369A. Pipelined output or flow-through mode is selected via the FT /PIPE pin.

Each port of CY7C09369A contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. 

A HIGH on CE ₀ or LOW on CE₁ for one clock cycle ofCY7C09369A  will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE ₀ LOW and CE ₁ HIGH to reactivate the outputs. 
   
Counter enable inputs of CY7C09369A are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe(ADS ). When the port's Count Enable (CNTEN ) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal.CY7C09369A  will read/write one word from/into each successive address location until CNTEN is deasserted. The counter CY7C09369A can address the entire memory array and will loop back to the start. Counter Reset (CNTRST ) is used to reset the burst counter.

All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.