CY7C09359

• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two Flow-Through/Pipelined devices
-4K x 18 organization (CY7C09349)
-8K x 18 organization (CY7C09359)
• Three Modes
-Flow-Through
-Pipelined
-Burst
• Pipelined output mode on both ports allows fast 100-MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5[1]/7.5/9/12 ns (max.)
• Low operating power
-Active = 200 mA (typical)
-Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
-Shorten cycle times
-Minimize bus noise
-Supported in Flow-Through and Pipelined modes
• Dual Chip enables for easy depth expansion
• Upper and lower byte controls for bus matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP R/WR

The CY7C09349 and CY7C09359 are high-speed synchronous CMOS 4K and 8K x 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.^[3] Registers on control, address, and data lines of CY7C09359 allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid t_CD2 = 6.5 ns^[1] (pipelined). Flow-through mode of CY7C09359 can also be used to bypass the pipelined output register to eliminate access latency. In flowthrough mode data of CY7C09359 will be available t_CD1 = 15 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin.

Each port of CY7C09359 contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto- HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE₀ or LOW on CE₁ for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables CY7C09359 allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE₀ LOW and CE₁ HIGH to reactivate the outputs.

Counter of CY7C09359 enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter of CY7C09359  can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter.

All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.