CY7C09355AV

The CY7C09349AV and CY7C09359AV are high-speed 3.3V synchronous CMOS 4K and 8K x 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memor2[2] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data of CY7C09355AV  is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register CY7C09355AV to eliminate access latency. In flowthrough mode data will be available tCD1 = 18 ns after the address is clocked into CY7C09355AV. Pipelined output or flowthrough mode is selected via the FT/Pipe pin.

Each port of CY7C09355AV contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto- HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times.